Driver circuits are critical components in a large number of applications, particularly memory applications. In general, a driver circuit has an output which is driven to a first voltage level to represent a data bit “1” and a second voltage level to represent a data bit “0.” The rate of change of the output signal voltage between data “0” and data “1” and data “1” and data “0” as a function of time is referred to as the “slew rate.”
Conventional driver circuits include a PMOS transistor coupled in series to an NMOS transistor. Typically, the gates of both transistors are tied together so that both transistors receive the same input signal. These driver circuits are designed such that the PMOS and NMOS transistors operate in a complementary fashion. That is, when the PMOS transistor is on, coupling a first supply voltage to the output, the NMOS transistor is off and when the NMOS transistor is on, coupling a second supply voltage to the output, the PMOS transistor is off. In some applications, both transistors may be off.
Many conventional driver circuits use high output swing CMOS transistors. However, these transistors are difficult to turn on and off in an optimal fashion. Thus, these conventional driver circuits are susceptible to a variety of phenomena which impact the quality of the output signal. For example, if the transition of the output signal from low to high and vice versa is too rapid, chip and board power distribution and signal interconnection are stressed, resulting in excessive ground bounce, cross talk, and signal ringing. If the transitions are too slow, timing errors in devices or circuits using the driver circuit output could occur.
In addition, if both transistors in the driver circuit are on simultaneously (e.g., when one or both transistors do not turn off rapidly enough), shoot-through currents occur. When both transistors are on, a substantial portion of the current sourced by the PMOS transistor flows through the NMOS transistor to the second supply voltage which is typically ground or a negative supply voltage. A shoot-through current causes wasted power, and drooping and ringing in the supply voltage.
The quality of the output signal is also impacted if both transistors are off at the same time. If both transistors are off simultaneously, flat spots occur in the output transitions. These flat spots may cause timing errors in devices and circuits coupled to the output of the driver circuit.
Many conventional driver circuits also include one or more predriver circuits designed to control the on and off transitions of the driver transistors. These predrivers are typically also CMOS field-effect transistors, like the driver transistors. Because the threshold voltage of the predriver transistors causes non-uniform time constant behavior over the switching range of the driver transistors, the predriver transistors have difficulty maintaining their characteristics over the full switching range of the driver transistors. Thus, the characteristics of the predriver transistors are dependent on supply voltage and process variations.
The maximum data rate supported by a driver circuit is important factor in its usability in certain applications. The maximum data rate of a driver circuit may be limited by the settling time of the circuit. Under certain conditions, the output signal may initially rise above the desired voltage value for a data “1” and then settle to the desired voltage value. The time required to reach the desired voltage is referred to as the settling time. If the settling of the gate control voltage, and therefore the output signal, is incomplete at the maximum data rate, then the driver delay and/or output voltage shape may vary with the data pattern, leading to an undesirable source of system timing errors.
Therefore, a need exists for a driver circuit having programmable gate control voltage time constants, with voltage clamping on the output transistor gates to allow for moderate slew rates, tight duty cycle control, and fast data rates.
A further need exists for a programmable slew rate control system having driver transistors which are turned on and off relative to each other with enough overlap for a smooth transition but not enough overlap to cause significant shoot-through current.
A need also exists for a programmable slew rate having a predriver circuit allowing for fine control of the on and off times of the driver transistors.